(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method and structure for creating a high Q inductor while simultaneously reducing the surface space that is consumed by such an inductor. The inductor of the invention is a spiral inductor that is positioned in a plane that is perpendicular to the plane of the substrate on which the conductor is created.
(2) Description of the Prior Art
Modern semiconductor technology requires the creation of high performance semiconductor devices that are produced at competitive prices. A direct result of these requirements is that device density and inter-device packaging density continue to increase from which directly follows the requirement that the surface area or space that is available on the surface of a semiconductor substrate is carefully allocated and maximized in its use.
While the majority of semiconductor devices relate to the field of digital data processing, electronic circuitry can nevertheless be divided into two broad fields. One field addresses digital processing while the second field addresses the manipulation of analog signals. Digital semiconductor devices have as function the manipulation or storage of digital information. The functions of analog electronic circuitry have in previous years typically been handled by separate components such as relatively large capacitors or relatively large inductors. The separate components may have been applied in combination with digital processing capabilities, whereby however a significant portion of the functional implementation has been realized by the use of for instance capacitive and inductive components in addition to and functionally collaborating with the digital components. Circuit requirements that are imposed on components that are required for analog processing have in the past limited the integration of such components into typical semiconductor integrated circuit devices.
Modern mobile communication applications center around compact high-frequency equipment. With the continued improvements in the performance characteristics of this equipment, continued emphasis will be placed on small size of the equipment, low power consumption, increased frequency applications and low noise levels. Semiconductor devices are used in the field of mobile communication for the creation of Radio Frequency (RF) amplifiers. A major component of a typical RF amplifier is a tuned circuit that contains inductive and capacitive components. The tuned circuit has as electrical characteristic that, dependent on and determined by the values of its inductive and capacitive components, can form an-impedance that is frequency dependent, which enables the tuned circuit to either form a high or a low impedance for signals of a certain frequency. In this manner the tuned circuit can either reject or pass and further amplify components of an analog signal based on the frequency of that component. The tuned circuit can therefore be used as a filter to filter out or remove signals of certain frequencies or to remove noise from a circuit configuration that is aimed at manipulating analog signals. The tuned circuit can also be used to form a high electrical impedance by using the LC resonance of the circuit and to thereby counteract the effect of parasitic capacitances that are part of a circuit. The self-resonance that is caused by the parasitic capacitance between the (spiral) inductor and the underlying substrate will limit the use of the inductor at high frequencies.
One of the key components that is applied in creating high frequency analog semiconductor devices is the inductor that forms part of a LC resonance circuit. The key challenge in the creation of the inductor is to minimize the surface area that is required for the creation of the inductor while maintaining a high Q value for the inductor. Conventional inductors that are created on the surface of a substrate are of a spiral shape, whereby the spiral is created in a plane that is parallel with the plane of the surface of the substrate. Conventional methods that are used to create the inductor on the surface of a substrate suffer several limitations. Most high Q inductors form part of a hybrid device configuration or of Monolithic Microwave Integrated Circuits (MMIC""s) or are created as discrete components, the creation of which is not readily integratable into a typical process of Integrated Circuit manufacturing.
By combining the creation on one semiconductor monolithic substrate of circuitry that is aimed at the function of analog data manipulation and analog data storage with the functions of digital data manipulation and digital data storage, a number of significant advantages are achieved. Such advantages include the reduction of manufacturing costs and the reduction of power consumption by the combined functions. To reach required inductive values for particular applications, inductors can be of significant physical size and can therefore require a significant surface area of the semiconductor substrate. To limit this impact of space requirement, inductors are typically formed on the surface of a substrate in a spiral form. The spiral form of the inductor however results in parasitic capacitances between the inductor wiring and the underlying substrate, due to the physical size of the inductor. These parasitic capacitances have a serious negative effect on the functionality of the created LC circuit by sharply reducing resonance frequency of the tuned circuit of the application.
Widely used in the industry to describe the applicability of a created inductor is the Quality (Q) factor of the inductor. The quality factor Q of an inductor is defined as follows: Q=Es/El wherein Es is the energy that is stored in the reactive portion of the component while El is the energy that is lost in the reactive portion of the component. The higher the quality of the component, the closer the resistive value of the component approaches zero while the Q factor of the component approaches infinity. The quality factor for components differs from the quality that is associated with filters or resonators. For components, the quality factor serves as a measure of the purity of the reactance (or the susceptance) of the component, which can be degraded due to parasitics. In an actual configuration, there are always some physical resistors that will dissipate power, thereby decreasing the power that can be recovered. The quality factor Q is dimensionless. A Q value of greater than 100 is considered very high for discrete inductors that are mounted on the surface of Printed Circuit Boards. For inductors that form part of an integrated circuit, the Q value is typically in the range between about 3 and 10.
In creating an inductor on a monolithic substrate on which additional semiconductor devices are created, the parasitic capacitances that occur as part of this creation limit to about 10 the quality factor that can be achieved for the inductor using the conventional silicon process. This limitation is, for many applications, not acceptable. Dependent on the frequency at which the LC circuit is designed to resonate, significantly larger values of quality factor, such as for instance 100 or more, must be available. Prior Art has in this been limited to creating values of higher quality factors as separate units, and in integrating these separate units with the surrounding device functions. This negates the advantages that can be obtained when using the monolithic construction of creating both the inductor and the surrounding devices on one and the same semiconductor substrate. The non-monolithic approach also has the disadvantage that additional wiring is required to interconnect the sub-components of the assembly, thereby again introducing additional parasitic capacitances and resistive losses over the interconnecting wiring network. For many of the applications of the RF amplifier, such as portable battery powered applications, power consumption is at a premium and must therefore be as low as possible. By raising the power consumption, the effects of parasitic capacitances and resistive power loss can be partially compensated but there are limitations to even this approach. These problems take on even greater urgency with the rapid expansion of wireless applications such as portable telephones and the like. Wireless communications is a rapidly expanding market, where the integration of RF integrated circuits is one of the most important challenges. One of the approaches is to significantly increase the frequency of operation to for instance the range of 10 to 100 GHz. For such high frequencies, the values of the quality factor obtained from silicon-based inductors are significantly degraded. For applications in this frequency range, monolithic inductors have been researched using other than silicon as the base for the creation of the inductors. Such monolithic inductors have for instance been created using sapphire or GaAs as a base. These inductors have a considerably lower parasitic capacitance than their silicon counterparts and therefore provide higher frequencies of resonance of the LC circuit. Where however more complex applications are required, the need still exists to create inductors using silicon as a substrate. For those applications, the approach of using a base material other than silicon has proven to be too cumbersome while for instance GaAs as a medium for the creation of semiconductor devices is as yet a technical challenge that needs to be addressed.
The incorporation of RF inductors without sacrificing device performance due to substrate losses has been extensively researched in recent years. Some of the techniques that have been used for this approach include:
the selective removing (by etching) of the silicon underneath the inductor (using methods of micro-machining) thereby removing substrate parasitic effects
using multiple layers of metal (such as aluminum) interconnects or of copper damascene interconnects
using a high resistivity silicon substrate thereby reducing resistive losses in the silicon substrate, since resistive substrate losses form a dominant factor in determining the Q value of silicon inductors
using metals that are particularly adaptable to the process of the formation of inductors, a concern is thereby however raised by the use of AlCu (a metal that is frequently used in semiconductor metallization) since AlCu has higher resistivity than gold (Au) metallization that is frequently used in GaAs technology
employing biased wells underneath a spiral conductor
inserting various types of patterned ground shields between the spiral inductor and the silicon substrate, and
creating an active inductive component that simulates the electrical properties of an inductor as it is applied in active circuitry; this approach however results in high power consumption by the inductor and in noise performance that is unacceptable for low power, high frequency applications
The above listing of researched alternatives is not meant to be complete or all inconclusive. The above approaches have as common objectives to:
1) enhance the quality (Q) value of the inductor
2) increase the frequency of the LC self-resonance thereby increasing the frequency range over which the inductor can be used, and
3) reduce the surface area that is required for the creation of the inductor.
The inductor of the invention addresses the objectives that have been listed above and provides for a method of creating an inductor that sharply reduces the surface area that is required for the inductor. The method of the invention creates a vertical spiral inductor, which has performance characteristics that differ sharply from the performance characteristics of a typical spiral inductor that is created in a plane that is parallel with the surface of the substrate. The vertical spiral inductor of the invention uses current processes of multilevel interconnect to create the return patterns of the spiral, the return patterns are vertical with respect to the plane of the surface of the substrate. The electromagnetic field of the vertical return sections of the spiral inductor limit the resistive losses that are typically obtained in the silicon substrate since the electromagnetic field of these return sections is essentially parallel to the surface of the substrate and does therefore not penetrate the substrate. In addition, the surface area that is required for the creation of the inductor is sharply reduced due to its vertical construction, that is vertical with respect to the plane of the surface of the substrate.
FIG. 1a shows a top view of a Prior Art horizontal spiral inductor 25. Some of the design parameters of conductor 25 are highlighted as follows:
10 is the body of the inductor and contains a conductive material
11 is one extremity of the conductive body 10 of the inductor 25 and is, for convenience sake and arbitrarily, referred to as the beginning of the conductive body 10 of the inductor
12 is a conductive connector that connects to the beginning 11 of the conductive body 10 of the inductor 25,
13 is the opposing extremity of the conductive body 10 of the inductor 25 and will be referred to as the end of the conductive body of the inductor
14 is a contact via that interconnects metal strip 12 with the conductive body 10 of the inductor
16 is the spacing between the spirals of the conductive body 10 of inductor 25
18 is the width of the spirals of the conductive body 10 of inductor 25
20 is the length of the longest spiral of the conductive body 10 of inductor 25, and
22 is the length of the shortest spiral of the conductive body 10 of inductor 25.
The top view of the Prior Art inductor that is shown in FIG. 1 is not shown in order to highlight in extensive detail all the parameters that can be associated with such an inductor but merely serves to point out the essence of the Prior Art inductor, that is:
the geometric shape of the inductor is that of a spiral
the individual sections that make up the spiral of the inductor alternately intersect at an angle of 90 degrees and have a length and a width and are separated by a spacing
the spiral that forms the inductor ends in two extremities, the inductor is electrically interconnected to surrounding circuitry by being connected to these two extremities, and
the body of the inductor is contained in a plane that is parallel to the plane of the surface of the substrate on which the inductor is created.
Not shown in FIG. 1 is the height of each of the linear segments that collectively form the body of the inductor 10, this height can be defined as the thickness of the conductive layer that is deposited on the surface of the substrate for the formation of the inductor. The lower surface of the inductor is the surface of the inductor that is parallel to the surface of the substrate and that is closest to the surface of the substrate, the upper surface of the inductor is the surface of the inductor that is parallel to the surface of the substrate and that is furthest removed from the surface of the substrate. The distance between the upper surface and the lower surface of the inductor as measured in a direction that is perpendicular to the plane of the substrate is the height of the inductor. A cross section of the inductor that is taken in a plane between the upper and the lower surface of the inductor shows the geometric shape of the inductor, which is the shape of a spiral. The height of the inductor of Prior Art is essentially the same along the spiral of the inductor.
U.S. Pat. No. 5,936,298 (Capocelli coil. teaches process for a Helix coil.
U.S. Pat. No. 5,576,680 (Ling) Structure and fabrication process of inductors on semiconductor chip, shows a vertical coil. See FIGS. 3e through 4c. Also a helix coil with a core.
U.S. Pat. No. 5,372,967 (Sundram)xe2x80x94Method for fabricating a vertical trench inductor, shows a vertical trench coil process.
U.S. Pat. No. 5,884,990 (Burghartz et al.) shows another vertical coil process.
A principle objective of the invention is to reduce the surface area that is required for the creation of an inductor on the surface of a silicon semiconductor substrate.
Another objective of the invention is to create an inductor on the surface of a silicon semiconductor substrate whereby the electromagnetic field of the inductor has sharply reduced resistive losses induced by the underlying substrate.
In accordance with the objectives of the invention a new method and structure is provided for the creation of an inductor on the surface of a silicon semiconductor substrate. The inductor is of spiral design, whereby the plane of a cross section of the inductor that reflects the spiral design of the inductor is perpendicular to the plane of the underlying substrate. The first embodiment of the invention provides a method of creating a vertical spiral inductor with thin conductor width. The second embodiment of the invention provides a method of creating a vertical spiral inductor with thin conductor width whereby ferromagnetic material is incorporated in the creation of the inductor. The third embodiment of the invention provides a method of creating a vertical spiral inductor with wide conductor width. The fourth embodiment of the invention provides a method of creating a vertical spiral inductor with wide conductor width whereby ferromagnetic material is incorporated in the creation of the inductor. The fifth embodiment of the invention provides two vertical spiral inductors that are connected in series. The sixth embodiment of the invention provides two vertical spiral inductors that are connected in series whereby ferromagnetic material is incorporated in the creation of the inductor. The seventh embodiment of the invention provides for the creation of a vertical spiral inductor that has a construction of protruding spirals. The eighth embodiment of the invention provides for the creation of a vertical spiral inductor that is combined with a horizontal spiral inductor whereby ferromagnetic materials are incorporated in the creation of the vertical inductor whereby the horizontal spiral inductor is overlaying the vertical spiral inductor. The ninth embodiment of the invention provides for the creation of a vertical spiral inductor that is combined with a horizontal spiral inductor whereby ferromagnetic materials are incorporated in the creation of the vertical inductor whereby the horizontal spiral inductor is in the plane of the top surface of the vertical spiral inductor.
FIG. 1 shows a top view of a Prior Art horizontal spiral conductor.
FIG. 2 addresses a vertical inductor of the invention that uses thin conductor width, as follow:
FIG. 2a is a right hand extended three-dimensional view of the vertical inductor of the invention with a small conductor width.
FIG. 2b shows a top view the vertical inductor of the invention with a small conductor width.
FIG. 2c shows a cross section in an Y-direction of the vertical inductor of the invention with a small conductor width.
FIG. 2d shows a cross section in a Z-direction of the vertical inductor of the invention with a small conductor width.
FIG. 3 addresses a vertical inductor of the invention that uses small conductor width whereby furthermore ferromagnetic material is incorporated, as follow:
FIG. 3a is a right hand extended three-dimensional view of the vertical inductor of the invention with a small conductor width whereby ferromagnetic material is incorporated.
FIG. 3b shows a top view the vertical inductor of the invention with a small conductor width whereby ferromagnetic material is incorporated.
FIG. 3c shows a cross section in an X-direction of the vertical inductor of the invention with a small conductor width whereby ferromagnetic material is incorporated.
FIG. 3d shows a cross section in an Y-direction of the vertical inductor of the invention with a small conductor width whereby ferromagnetic material is incorporated.
FIG. 4 is a right hand extended three-dimensional view of the vertical inductor of the invention with a large conductor width.
FIG. 5 is a right hand extended three-dimensional view of the vertical inductor of the invention with a large conductor width whereby ferromagnetic material is incorporated.
FIG. 6 addresses a vertical inductor of the invention whereby two vertical spiral inductors are connected in series, as follow:
FIG. 6a is a right hand extended three-dimensional view of vertical inductor of the invention whereby two vertical spiral inductors are connected in series.
FIG. 6b shows a top view the vertical inductor of the invention whereby two vertical spiral inductors are connected in series.
FIG. 6c shows a cross section in an X-direction of the vertical inductor of the invention whereby two vertical spiral inductors are connected in series.
FIG. 6d shows a cross section in an Y-direction of the vertical inductor of the invention whereby two vertical spiral inductors are connected in series.
FIG. 7 is a right hand extended three dimensional view of vertical inductor of the invention whereby two vertical spiral inductors are connected in series whereby furthermore ferromagnetic material is incorporated.
FIG. 8 addresses an inductor of the invention whereby the spirals of the inductor protrude from the vertical plane of the inductor, as follows:
FIG. 8a shows an expanded three-dimensional front side view of a vertical inductor of the invention whereby the spirals of the inductor progressively protrude from the body of the inductor.
FIG. 8b shows an expanded three-dimensional backside view of a vertical inductor of the invention whereby the spirals of the inductor progressively protrude from the body of the inductor.
FIG. 8c shows a cross section in an X-dimension of a vertical inductor of the invention whereby the spirals of the inductor progressively protrude from the body of the inductor.
FIG. 9 addresses an inductor of the invention whereby a conventional horizontal spiral inductor is combined with a vertical spiral inductor of the invention whereby the horizontal inductor overlays the vertical inductor, as follows:
FIG. 9a shows a three-dimensional expanded right hand view of an inductor of the invention whereby a horizontal spiral inductor is connected in series with a vertical spiral inductor.
FIG. 9b shows a cross section taken in a plane that is perpendicular with the surface of the underlying substrate of an inductor of the invention whereby a horizontal spiral inductor is connected in series with a vertical spiral inductor.
FIG. 10 addresses an inductor of the invention whereby a conventional horizontal spiral inductor is combined with a vertical spiral inductor of the invention whereby the horizontal inductor is located in the plane of the top layer of the vertical inductor, as follows:
FIG. 10a shows a three dimensional expanded right hand view of an inductor of the invention whereby a horizontal spiral inductor is connected in series with a vertical spiral inductor whereby furthermore the horizontal inductor is located in the plane of the top layer of the vertical inductor.
FIG. 10b shows a cross section taken in an X-direction in a plane that is perpendicular with the surface of the underlying substrate of an inductor of the invention whereby a horizontal spiral inductor is connected in series with a vertical spiral inductor whereby furthermore the horizontal inductor is located in the plane of the top layer of the vertical inductor.